Semi-synchronous receiver and apparatus for reading information

ABSTRACT

A receiver is described for delivering a data sequence (ak) at a data rate 1/T from an analog signal (Sa), the receiver comprising: a) converting means ( 40 ) for generating a received sequence (rn) by sampling the analog signal (Sa) with a sample rate of 1/Ts, whereby the sample rate 1/Ts of the received sequence (rn) is controllable by a preset value (Pv); b) digital processing means ( 12 ) for delivering a processed sequence (yn) by processing the received sequence (rn); c) a first sample rate converter ( 13 ) for converting the processed sequence (yn) into an equivalent processed sequence (ye) at the data rate 1/T, whereby the data rate of the equivalent processed sequence (ye) is controllable by a control signal (Sc); d) an error generator ( 14 ) for delivering an error sequence (ek) from the equivalent processed sequence (ye); e) a control signal generating means ( 15 ) for generating the control signal (Sc) dependent on the error sequence (ek); f) a detector ( 16 ) for deriving the data sequence (ak) from the equivalent processed sequence (ye),whereby the ratio between the sample rates 1/T and 1/Ts is substantially constant. Conventional synchronous receivers which comprise a Sample Rate Converter have the disadvantage that the digital processing is performed within the control loop of the SRC. The delay resulting from the digital processing contributes to the overall delay of the loop, which can lead to instabilities, especially when high bandwidths are require. Therefore the receiver of the invention does the digital processing outside the control loop. To keep the advantage that the digital processing can be done at a fixed rate, the converting means ( 40 ) are controlled by a preset value for keeping the ratio T/Ts constant.

The invention relates to a receiver for delivering a data sequence at adata rate 1/T from an analog signal.

The invention further relates to an apparatus for reading informationfrom an information track on an information carrier.

A receiver for delivering a data sequence can be used in an optical discplayer. In the optical disc player an analog replay signal is retrievedfrom an optical disc. An optical head retrieves the analog replay signalby using a laser. After some analog processing the replay signal isprovided to Converting means such as an Analog to Digital converter(ADC). The ADC is controlled by a clock which comes from a VoltageControlled Oscillator (VCO). The frequency of the clock that is providedby the VCO is dependent on the output of an error generator. The errorgenerator generates an error signal from an output of digital processingmeans (DPM). The DPM can be an equalizer for instance. The DPM processesthe output signal of the ADC. Finally the output of the DPM is fed to adetector to produce the data sequence. All the processing after the ADCis done synchronous with a data rate 1/T of the data sequence.

As receivers for digital recording and transmission are increasinglyimplemented digitally, the VCO based timing recovery is replaced by atiming recovery using a sample rate converter (SRC). The first part ofthis receiver also consists of analog processing means and an ADC. TheADC in this receiver is controlled by a free running clock. The freerunning clock usually is a crystal based clock. The frequency of theclock is independent on the data rate 1/T of the data sequence. Theoutput of the ADC is fed to the sample rate converter (SRC). The SRC iscontrolled by a Numerical Controlled Oscillator (NCO). The frequency ofthe output signal of the NCO is dependent on the output signal of anerror generator. The error generator reacts on an output of digitalprocessing means (DPM). Again the output of the DPM is fed to a detectorto generate the data sequence. The advantage of such synchronouslysampled receivers is that the digital signal processing like equalizingfor instance, can be done in the symbol rate clock domain retrieved bythe timing recovery. On the other hand the delay resulting from thisprocessing contributes to the overall delay of the loop, which can leadto instabilities, especially when high bandwidths are required. Thishighly constrains the digital processing used in the loop and thereforethe performance can potentially severely be degraded.

It is a goal of the invention to provide a receiver which circumventsthe above-mentioned problem.

It is a further object of the invention to provide an apparatus forreading information which circumvents the above-mentioned problem.

This goal is achieved with a receiver for delivering a data sequence ata data rate 1/T from an analog signal, the receiver comprising:

converting means for generating a received sequence by sampling theanalog signal with a sample rate of 1/Ts, whereby the sample rate 1/Tsof the received sequence is controllable by a preset value;

digital processing means for delivering a processed sequence byprocessing the received sequence;

a first sample rate converter for converting the processed sequence intoan equivalent processed sequence at the data rate 1/T, whereby the datarate of the equivalent processed sequence is controllable by a controlsignal;

an error generator for delivering an error sequence from the equivalentprocessed sequence;

a control signal generating means for generating the control signaldependent on the error sequence;

a detector for deriving the data sequence from the equivalent processedsequence,

whereby the preset value is set to a value wherein the ratio between thesample rates 1/T and 1/Ts is substantially constant.

The further object is achieved by an apparatus for reading informationfrom an information track on an information carrier, which contains:

means for retrieving the information from the information carrier andoutputting an analog signal;

a receiver for delivering a data sequence at a data rate 1/T from ananalog signal, the receiver comprising:

converting means for generating a received sequence by sampling theanalog signal with a sample rate of 1/Ts, whereby the sample rate 1/Tsof the received sequence is controllable by a preset value;

digital processing means for delivering a processed sequence byprocessing the received sequence;

a first sample rate converter for converting the processed sequence intoan equivalent processed sequence at the data rate 1/T, whereby the datarate of the equivalent processed sequence is controllable by a controlsignal;

an error generator for delivering an error sequence from the equivalentprocessed sequence;

a control signal generating means for generating the control signaldependent on the error sequence;

a detector for deriving the data sequence from the equivalent processedsequence,

whereby the preset value is set to a value wherein the ratio between thesample rates 1/T and 1/Ts is substantially constant.

Starting from the known receiver topology with an SRC as describedbefore, the digital processing block is moved from its position insidethe timing recovery to the asynchronous domain, i.e. between the Analogto Digital Converter ADC and the SRC. Because the processing ispositioned in the asynchronous domain, its time span depends now on theover-sample ratio T/Ts, resulting in an oversample dependentperformance. Instead of a free running clock the ADC can be controlledby a preset value. The preset value controls the rate at which the ADCmakes samples. The preset value is chosen such that the T/Ts ratio hasfixed value, a few percents of deviation is possible. The timingrecovery, which transfers the signals from the asynchronous Ts domain tothe data-rate domain, can be optimized employing the fixed T/Ts ratio.Instead of an ADC controlled by the preset value, also an ADC controlledby a free running clock combined with a second SRC can be used, wherethe ADC outputs an intermediate received sequence. The second SRCconverts the intermediate received sequence into the received sequence,where the sample rate is controlled by the preset value. The combinationof the ADC with the second SRC results in the same received sequencecompared to the preset value controlled ADC.

In a further embodiment of the invention the receiver comprises lock aidmeans for keeping the ratio between the sample rates 1/T and 1/Tssubstantially constant by generating the preset value of either thepreset value controlled ADC or of the second sample rate converter.There are different ways for the lock aid means to realize this. Forinstance, the lock aid means can generate the preset value by keeping anaverage number of transitions of the equivalent received sequence inrelation to the data rate 1/T substantially constant. The data consistsof bit-streams which usually have maximum run-lengths, i.e. a maximumnumber of subsequent zeros or ones. In a bit-stream of a certain lengththe average number of transitions will therefore be substantiallyconstant. By using this average number as a control parameter for thepreset value, the lock aid means are able to keep the sample rates 1/Tand 1/Ts substantially constant.

If the receiver is used in an apparatus for reading information from aninformation track on an information carrier, where the information trackcomprises a wobble having a wobble-frequency related to the data rate1/T, the lock aid means are able to generate the preset value as afunction of the wobble-frequency. For instance, in the DVD+RW format awobble is present on the DVD disc. The wobble is synchronous to the dataon the DVD. The lock aid means can therefore use the wobble signal tokeep the sample rates 1/T and 1/Ts substantially constant, for instanceby fixing the ratio between the wobble-frequency and the sample rate1/Ts.

These and other aspects of the invention will be apparent from andelucidated further with reference to the embodiments described by way ofexample in the following description and with reference to theaccompanying drawings, in which

FIG. 1 shows a prior art receiver;

FIG. 2 shows a prior art receiver with a sample rate converter;

FIG. 3 shows a receiver according to the invention;

FIG. 4 shows an other embodiment of the receiver of the invention;

FIG. 5 shows an embodiment of an apparatus for reading information froman information track on an information carrier;

FIG. 6 shows an example of an information carrier with an informationtrack thereon;

FIG. 7 a and FIG. 7 b show a bode diagram of a receiver with loop delay;

FIG. 8 shows two step responses of a receiver with and without loopdelays;

FIG. 9 a shows a frequency response of the classical timing recoverywith delays at high bandwidths;

FIG. 9 a shows a frequency response of the classical timing recoverywith delays at low bandwidths;

FIG. 9 c shows a frequency response of the receiver according to theinvention at high bandwidths.

FIG. 10 shows an embodiment of the receiver according to the inventionwith lock aid means.

The prior art receiver depicted in FIG. 1 has converting means 40 toconvert an analog signal Sa into a received sequence r_(n). Theconverting means 40 usually are Analog to Digital Converters (ADC). TheADC samples the analog signal Sa at a sample rate 1/Tc and the samplerate is controlled by a Voltage Controlled Oscillator 30. The VCO formsa phase locked loop (PLL) together with an error generator 14. Theoutput of the VCO has a frequency dependent on a voltage level at aninput. In FIG. 1 an output of the error generator 14 controls thefrequency of the VCO. The received sequence r_(n) is processed by thedigital processing means 12. The digital processing means 12 can forinstance be an equalizer to equalize the received sequence r_(n). Theresult of the digital processing is a processed sequence y_(n). Theprocessed sequence y_(n) is fed to the error generator 14 and to adetector 16. The detector 16 derives the data sequence a_(k) from theprocessed sequence y_(n).

In FIG. 2 the VCO based timing recovery is converted to a timingrecovery using a sample rate converter 13 (SRC). The converting means 40are now controlled by a free running clock FC. The frequency of theclock is independent of the data rate 1/T of the data sequence a_(k).The SRC is controlled by control signal generating means 15. The controlsignal generating means 15 can for instance be a Numerical ControlledOscillator (NCO). The frequency of the output signal of the NCO isdependent on the output signal of the error generator 14. The advantageof such synchronously sampled receivers is that the digital processingby the digital processing means 12 can be done in the symbol rate clockdomain retrieved by the timing recovery. On the other hand the delayresulting from this processing contributes to the overall delay of theloop, which can lead to instabilities, especially when high bandwidthsare required. This highly constrains the digital processing used in theloop and therefore the performance can potentially severely be degraded.

To eliminate the delay, the digital processing block 12 can be movedfrom its position inside the timing recovery to the asynchronous domainTs as depicted in FIG. 3. Now the digital processing means 12 ispositioned between the converting means 40 and the sample rate converter13. Because the processing is positioned in the asynchronous domain, itstime span depends now on the over-sample ratio T/Ts, resulting in anoversample dependent performance. Therefore, in the receiver accordingto the invention, instead of using a free running clock FC to controlthe sample ratio of the converting means 40, a preset value Pv is usedto control the sample ratio of the converting means 40. The preset valuePv is chosen such that the T/Ts ratio has fixed value, a few percents ofdeviation is possible. The timing recovery, which transfers the signalsfrom the asynchronous Ts domain to the data-rate domain, can beoptimized employing the fixed T/Ts ratio.

The converting means 40 can be realized with an ADC operating at asample rate which is controllable by the preset value Pv. Alternatively,the converting means 40 can be realized with an ADC 41 controlled by afree running clock FC combined with an SRC 42 as depicted in FIG. 4. InFIG. 4 the converting means 40 comprises an ADC 41 and a second samplerate converter 42. The ADC 41 converts the analog signal Sa into anintermediate received sequence r_(i). After the ADC 41 the second samplerate converter 42 converts the intermediate received sequence r_(i) intothe received sequence r_(n) at a sample rate 1/Ts controlled by thepreset value Pv.

In FIG. 5 an apparatus for reading information is depicted. In FIG. 6 aninformation carrier 21 with an information track 20 is shown. Theapparatus in FIG. 5 comprises rotation means 23 to rotate theinformation carrier 21. Furthermore, the apparatus comprises means 22for retrieving the information from the information carrier 21. In a CDplayer for instance, the means 22 comprise an optical pickup unit (OPU).The OPU generates a laserbeam that is projected on the surface of theinformation carrier 21. The laserbeam is reflected by the surface of theinformation carrier 21 and projected by the OPU on detection means. Thedetection means generate the analog signal Sa. The signal coming fromthe detection means can also be pre-processed by analog processing meansbefore the analog signal Sa is outputted.

As a test case the above-mentioned principle is tried on the fullydigital receiver used in optical read-out systems. The starting point isthe receiver of FIG. 2 where the converting means 40 consist of an ADC,and the digital processing means 12 consist of a finite impulse response(FIR) filter or equalizer. The control generating means 15 consist of anumerically controlled oscillator. Because the equalizer is positionedinside the loop, it equalizes the signal always in the symbol ratedomain. However its delay consisting of an intrinsic delay and of apipelining delay contributes to the overall delay of the loop which canlead to instabilities, especially when high bandwidths are required.This highly constrains the equalizer applicable in the loop.

In FIG. 7 b the decrease in phase margin when delays are added in theloop can be seen. On the horizontal axis in FIGS. 7 a and 7 b thenormalized frequency is depicted, where the normalized frequency is thefrequency in relation to the sample frequency. The vertical axis in FIG.7 a represents the magnitude of the transfer-function in decibel of thereceiver. The vertical axis in FIG. 7 b represents the phase in degrees.The full line in FIG. 7 b is the phase graph of the receiver withoutdelays, and the dotted line is the phase graph of the receiver withdelays.

In FIG. 8 the step-response of the loop with and without delays isshown. The dotted line is the step-response with delay and the full linethe step-response without delay. On the horizontal axis the elapsed timein synchronous bitclock periods is depicted and on the vertical axis theamplitude is represented.

In addition the frequency response of the classical timing recovery withdelays is shown at high and low bandwidth in FIG. 9 a and FIG. 9 brespectively. On the horizontal axis the elapsed time in fixed clockperiod is set out and on the vertical axis the normalized frequency,i.e. (1/T), is set out. It is obvious that with a large amount of delaysinside the loop doesn't allow high bandwidths.

From these plots one can easily derive that the amount of delays canseverely degrade the performance of the system. Therefore the order orthe time span of the FIR filter inside the loop is highly constrainedwhich can result in degraded performance.

In FIG. 9 c the frequency response at high bandwidths of the receiveraccording to the invention is shown. Here, the vertical axis representsthe ratio T/Ts. The converting means 40 consist of an ADC, and thedigital processing means 12 consist of an equalizer. The preset ischosen such that the T/Ts ratio has fixed value: the equalizer has now afixed time span independent on the oversample ratio of the data rateclock 1/T and the free running clock FC. Hence the performance will beindependent on the position on the disc in CAV (Constant AngularVelocity) mode.

The preset value Pv can be determined using lock aid means. A receiverwith lock aid means 17 is depicted in FIG. 10. The lock aid means 17 inFIG. 10 is a so-called Transition probability lock aid. The preset valuePv is driven such that the average number of transitions per bit clockmeasured after the converting means 40 is a fixed fraction. Thisfraction depends on the modulation code used. The lock aid means 17 havea wide capture without false locks, but is inherently slow since a largenumber of transitions must be observed.

The lock aid means 17 can also lock on the wobble frequency. The presetvalue Pv is driven by the wobble frequency. These lock aid means 17 canonly be used in optical disc formats that have a wobble with a frequencyrelated to the bit frequency. Practically this is suitable for the allrecordable/rewritable formats.

The timing recovery, which transfers the signals from thesemi-asynchronous Ts domain to the data-rate domain, can be optimizedemploying the fixed T/Ts ratio. It is of no use to design a timingrecovery which can convert a wide range of oversample ratios. Theoptimization can lead an even smaller loop delay.

The timing recovery is now directly driven by the zerocrossinginformations, resulting in a system with a small capture range and areduced amount of loop delay.

This invention proposes an alternative structure for the ‘synchronous’digital read-out receiver. This new semi-synchronous receiver topologystill has the advantage of frequency scalability without introducingconstraints to the digital processing. Therefore it is very suitable forhigh density/capacity optical disc formats, which acquire advancedsignal processing in order to detect the bits accurately.

1. Receiver for retrieving a data sequence (a_(k)) at a data rate 1/Tfrom an analog signal (Sa), the receiver comprising: converting means(40) for generating a received sequence (r_(n)) by sampling the analogsignal (Sa) with a sample rate of 1/Ts, whereby the sample rate 1/Ts ofthe received sequence (r_(n)) is controllable by a preset value (Pv);digital processing means (12) for delivering a processed sequence(y_(n)) by processing the received sequence (r_(n)); a first sample rateconverter (13) for converting the processed sequence (y_(n)) into anequivalent processed sequence (y_(e)) at the data rate 1/T, whereby thedata rate of the equivalent processed sequence (y_(e)) is controllableby a control signal (Sc); an error generator (14) for delivering anerror sequence (e_(k)) from the equivalent processed sequence (y_(e)); acontrol signal generating means (15) for generating the control signal(Sc) dependent on the error sequence (e_(k)); a detector (16) forderiving the data sequence (a_(k)) from the equivalent processedsequence (y_(e)), whereby the preset value (Pv) is set to a valuewherein the ratio between the sample rates 1/T and 1/Ts is substantiallyconstant.
 2. Receiver as claimed in claim 1, characterized in that theconverting means (40) comprises an analog to digital converter (41) forgenerating an intermediate received sequence (r_(i)) by sampling theanalog signal (Sa) at a clock rate 1/Tc, asynchronous to the data rate1/T, and a second sample rate converter (42) for converting theintermediate received sequence (r_(i)) into the received sequence(r_(n)) with a sample rate of 1/Ts, whereby the sample rate 1/Ts of thereceived sequence (r_(n)) is controllable by the preset value (Pv); 3.Receiver as claimed in claim 1 or 2, characterized in further comprisinglock aid means (17) for keeping the ratio between the sample rates 1/Tand 1/Ts substantially constant by generating the preset value (Pv). 4.Receiver as claimed in claim 3, characterized in that the lock aid means(17) are able to generate the preset value (Pv) such that an averagenumber of transitions of the equivalent received sequence (r_(e)) inrelation to the data rate 1/T is substantially constant.
 5. Apparatusfor reading information from an information track (20) on an informationcarrier (21), characterized in comprising: means (22) for retrieving theinformation from the information carrier and outputting an analog signal(Sa); a receiver for delivering a data sequence (a_(k)) at a data rate1/T from the analog signal (Sa) according to one of the claims 1 to 4.6. Apparatus as claimed in claim 5 as far as dependent on claims 1 to 3,characterized in that the information track (20) comprises a wobblehaving a wobble-frequency related to the data rate 1/T, and in that thelock aid means (17) are able to generate the preset value as a functionof the wobble-frequency.